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79c940 ? 2013 rochester electronics, llc. all rights reserved 03112013 specifcation number 79c940b-ci (a) rev c page 1 of 13 final publication# 16235 rev: e amendment/ 0 i s sue date : m ay 2 0 00 am79c940 media access controller for ethernet (mace?) distinctive characteristics integrated controller with manchester encoder/decoder and 10base-t transceiver and aui port supports ieee 802.3/ansi 8802-3 and ethernet standards 84-pin plcc and 100-pin pqfp packages 80-pin thin quad flat pack (tqfp) package available for space critical applications such as pcmcia modular architecture allows easy tuning to specific applications high speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer individual transmit (136 byte) and receive (128 byte) flfos provide increase of system latency and support the following features: automatic retransmission with no fifo reload automatic receive stripping and transmit padding (individually programmable) automatic runt packet rejection automatic deletion of collision frames automatic retransmission with no fifo reload direct slave access to all on board configuration/status registers and transmit/ receive flfos direct fifo read/write access for simple interface to dma controllers or l/o processors arbitrary byte alignment and little/big endian memory interface supported internal/external loopback capabilities external address detection interface (eadi ? ) for external hardware address filtering in bridge/router applications jtag boundary scan (ieee 1149.1) test access port interface for board level production test integrated manchester encoder/decoder digital attachment interface (dai ? ) allows by-passing of differential attachment unit interface (aui) supports the following types of network interface: aui to external 10base2, 10base5 or 10base-f mau dai port to external 10base2, 10base5, 10base-t, 10base-f mau general purpose serial interface (gpsi) to external encoding/decoding scheme internal 10base-t transceiver with automatic selection of 10base-t or aui port sleep mode allows reduced power consump- tion for critical battery powered applications 5 mhz-25 mhz system clock speed support for operation in industrial temperature range ( C 40 c to +85 c) available in all three packages general description the media access controller for ethernet (mace) chip is a cmos vlsi device designed to provide flexibility in customized lan design. the mace device is specif- ically designed to address applications where multiple i/o peripherals are present, and a centralized or sys- tem specific dma is required. the high speed, 16-bit synchronous system interface is optimized for an exter- nal dma or i/o processor system, and is similar to many existing peripheral devices, such as scsi and serial link controllers. the mace device is a slave register based peripheral. all transfers to and from the system are performed using simple memory or i/o read and write commands. in conjunction with a user defined dma engine, the mace chip provides an ieee 802.3 interface tailored to a specific application. its superior modular architec- ture and versatile system interface allow the mace device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. table 5 specification number: 79c940-ci (a) rev - page 1 of 13 final publication# 16235 rev: e amendment/ 0 i s sue date : m ay 2 0 00 am79c940 media access controller for ethernet (mace?) distinctive characteristics integrated controller with manchester encoder/decoder and 10base-t transceiver and aui port supports ieee 802.3/ansi 8802-3 and ethernet standards 84-pin plcc and 100-pin pqfp packages 80-pin thin quad flat pack (tqfp) package available for space critical applications such as pcmcia modular architecture allows easy tuning to specific applications high speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer individual transmit (136 byte) and receive (128 byte) flfos provide increase of system latency and support the following features: automatic retransmission with no fifo reload automatic receive stripping and transmit padding (individually programmable) automatic runt packet rejection automatic deletion of collision frames automatic retransmission with no fifo reload direct slave access to all on board configuration/status registers and transmit/ receive flfos direct fifo read/write access for simple interface to dma controllers or l/o processors arbitrary byte alignment and little/big endian memory interface supported internal/external loopback capabilities external address detection interface (eadi ? ) for external hardware address filtering in bridge/router applications jtag boundary scan (ieee 1149.1) test access port interface for board level production test integrated manchester encoder/decoder digital attachment interface (dai ? ) allows by-passing of differential attachment unit interface (aui) supports the following types of network interface: aui to external 10base2, 10base5 or 10base-f mau dai port to external 10base2, 10base5, 10base-t, 10base-f mau general purpose serial interface (gpsi) to external encoding/decoding scheme internal 10base-t transceiver with automatic selection of 10base-t or aui port sleep mode allows reduced power consump- tion for critical battery powered applications 5 mhz-25 mhz system clock speed support for operation in industrial temperature range ( C 40 c to +85 c) available in all three packages general description the media access controller for ethernet (mace) chip is a cmos vlsi device designed to provide flexibility in customized lan design. the mace device is specif- ically designed to address applications where multiple i/o peripherals are present, and a centralized or sys- tem specific dma is required. the high speed, 16-bit synchronous system interface is optimized for an exter- nal dma or i/o processor system, and is similar to many existing peripheral devices, such as scsi and serial link controllers. the mace device is a slave register based peripheral. all transfers to and from the system are performed using simple memory or i/o read and write commands. in conjunction with a user defined dma engine, the mace chip provides an ieee 802.3 interface tailored to a specific application. its superior modular architec- ture and versatile system interface allow the mace device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. table 5 specification number: 79c940-ci (a) rev - page 1 of 13 rochester electronics guarantees performance of its semiconductor products to the original oem specifcations. typical values are for reference purposes only. certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. rochester electronics reserves the right to make changes without further notice to any specifcation herein. for complete rochester ordering guide, please refer to page 3 please consult factory for specifc package availability
page 2 of 13 2 am79c940 the mace device provides a complete ethernet node solution with an integrated 10base-t transceiver, and supports up to 25-mhz system clocks. the mace device embodies the media access control (mac) and physical signaling (pls) sub-layers of the ieee 802.3 standard, and provides an ieee defined attach- ment unit interface (aui) for coupling to an external medium attachment unit (mau). the mace device is compliant with 10base2, 10base5, 10base-t, and 10base-f transceivers. additional features also enhance over-all system design. the individual transmit and receive fifos optimize system overhead, providing substantial latency during packet transmission and reception, and minimizing intervention during normal network error recovery. the integrated manchester encoder/decoder eliminates the need for an external serial interface adapter (sia) in the node system. if support for an external encoding/decoding scheme is desired, the general purpose serial interface (gpsi) allows direct access to/from the mac. in addition, the digital attach- ment interface (dai), which is a simplified electrical attachment specification, allows implementation of maus that do not require dc isolation between the mau and dte. the dai port can also be used to indicate transmit, receive, or collision status by connecting leds to the port. the mace device also provides an external address detection interface (eadi) to allow external hardware address filtering in internet working applications. the am79c940 mace chip is offered in a plastic leadless chip carrier (84-pin plcc), a plastic quad flat package (100-pin pqfp), and a thin quad flat package (tqfp 80-pin). there are several small func- tional and physical differences between the 80-pin tqfp and the 84-pin plcc and 100-pin pqfp config- urations. because of the smaller number of pins in the tqfp configuration versus the plcc configuration, four pins are not bonded out. though the die is identical in all three package configurations, the removal of these four pins does cause some functionality differ- ences between the tqfp and the plcc and pqfp configurations. depending on the application, the removal of these pins will or will not have an effect. (see section: ? pins removed for tqfp package and their effects.) with the rise of embedded networking applications op- erating in harsh environments where temperatures may exceed the normal commercial temperature (0 c to +70 c) window, an industrial temperature (-40 c to +85 c) version is available in all three packages; 84- pin plcc, 100-pin pqfp and 80-pin tqfp. the indus- trial temperature version of the mace ethernet control- ler is characterized across the industrial temperature range (-40 c to +85 c) within the published power supply specification (4.75 v to 5.25 v; i.e., 5% v cc ). thus, conformance of mace performance over this temperature range is guaranteed by the design and characterization monitor. table 5 specification number: 79c940-ci (a) rev - page 2 of 13 2 am79c940 the mace device provides a complete ethernet node solution with an integrated 10base-t transceiver, and supports up to 25-mhz system clocks. the mace device embodies the media access control (mac) and physical signaling (pls) sub-layers of the ieee 802.3 standard, and provides an ieee defined attach- ment unit interface (aui) for coupling to an external medium attachment unit (mau). the mace device is compliant with 10base2, 10base5, 10base-t, and 10base-f transceivers. additional features also enhance over-all system design. the individual transmit and receive fifos optimize system overhead, providing substantial latency during packet transmission and reception, and minimizing intervention during normal network error recovery. the integrated manchester encoder/decoder eliminates the need for an external serial interface adapter (sia) in the node system. if support for an external encoding/decoding scheme is desired, the general purpose serial interface (gpsi) allows direct access to/from the mac. in addition, the digital attach- ment interface (dai), which is a simplified electrical attachment specification, allows implementation of maus that do not require dc isolation between the mau and dte. the dai port can also be used to indicate transmit, receive, or collision status by connecting leds to the port. the mace device also provides an external address detection interface (eadi) to allow external hardware address filtering in internet working applications. the am79c940 mace chip is offered in a plastic leadless chip carrier (84-pin plcc), a plastic quad flat package (100-pin pqfp), and a thin quad flat package (tqfp 80-pin). there are several small func- tional and physical differences between the 80-pin tqfp and the 84-pin plcc and 100-pin pqfp config- urations. because of the smaller number of pins in the tqfp configuration versus the plcc configuration, four pins are not bonded out. though the die is identical in all three package configurations, the removal of these four pins does cause some functionality differ- ences between the tqfp and the plcc and pqfp configurations. depending on the application, the removal of these pins will or will not have an effect. (see section: ? pins removed for tqfp package and their effects.) with the rise of embedded networking applications op- erating in harsh environments where temperatures may exceed the normal commercial temperature (0 c to +70 c) window, an industrial temperature (-40 c to +85 c) version is available in all three packages; 84- pin plcc, 100-pin pqfp and 80-pin tqfp. the indus- trial temperature version of the mace ethernet control- ler is characterized across the industrial temperature range (-40 c to +85 c) within the published power supply specification (4.75 v to 5.25 v; i.e., 5% v cc ). thus, conformance of mace performance over this temperature range is guaranteed by the design and characterization monitor. table 5 specification number: 79c940-ci (a) rev - page 2 of 13 final publication# 16235 rev: e amendment/ 0 i s sue date : m ay 2 0 00 am79c940 media access controller for ethernet (mace?) distinctive characteristics integrated controller with manchester encoder/decoder and 10base-t transceiver and aui port supports ieee 802.3/ansi 8802-3 and ethernet standards 84-pin plcc and 100-pin pqfp packages 80-pin thin quad flat pack (tqfp) package available for space critical applications such as pcmcia modular architecture allows easy tuning to specific applications high speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer individual transmit (136 byte) and receive (128 byte) flfos provide increase of system latency and support the following features: automatic retransmission with no fifo reload automatic receive stripping and transmit padding (individually programmable) automatic runt packet rejection automatic deletion of collision frames automatic retransmission with no fifo reload direct slave access to all on board configuration/status registers and transmit/ receive flfos direct fifo read/write access for simple interface to dma controllers or l/o processors arbitrary byte alignment and little/big endian memory interface supported internal/external loopback capabilities external address detection interface (eadi ? ) for external hardware address filtering in bridge/router applications jtag boundary scan (ieee 1149.1) test access port interface for board level production test integrated manchester encoder/decoder digital attachment interface (dai ? ) allows by-passing of differential attachment unit interface (aui) supports the following types of network interface: aui to external 10base2, 10base5 or 10base-f mau dai port to external 10base2, 10base5, 10base-t, 10base-f mau general purpose serial interface (gpsi) to external encoding/decoding scheme internal 10base-t transceiver with automatic selection of 10base-t or aui port sleep mode allows reduced power consump- tion for critical battery powered applications 5 mhz-25 mhz system clock speed support for operation in industrial temperature range ( C 40 c to +85 c) available in all three packages general description the media access controller for ethernet (mace) chip is a cmos vlsi device designed to provide flexibility in customized lan design. the mace device is specif- ically designed to address applications where multiple i/o peripherals are present, and a centralized or sys- tem specific dma is required. the high speed, 16-bit synchronous system interface is optimized for an exter- nal dma or i/o processor system, and is similar to many existing peripheral devices, such as scsi and serial link controllers. the mace device is a slave register based peripheral. all transfers to and from the system are performed using simple memory or i/o read and write commands. in conjunction with a user defined dma engine, the mace chip provides an ieee 802.3 interface tailored to a specific application. its superior modular architec- ture and versatile system interface allow the mace device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. table 5 specification number: 79c940-ci (a) rev - page 1 of 13 final publication# 16235 rev: e amendment/ 0 i s sue date : m ay 2 0 00 am79c940 media access controller for ethernet (mace?) distinctive characteristics integrated controller with manchester encoder/decoder and 10base-t transceiver and aui port supports ieee 802.3/ansi 8802-3 and ethernet standards 84-pin plcc and 100-pin pqfp packages 80-pin thin quad flat pack (tqfp) package available for space critical applications such as pcmcia modular architecture allows easy tuning to specific applications high speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer individual transmit (136 byte) and receive (128 byte) flfos provide increase of system latency and support the following features: automatic retransmission with no fifo reload automatic receive stripping and transmit padding (individually programmable) automatic runt packet rejection automatic deletion of collision frames automatic retransmission with no fifo reload direct slave access to all on board configuration/status registers and transmit/ receive flfos direct fifo read/write access for simple interface to dma controllers or l/o processors arbitrary byte alignment and little/big endian memory interface supported internal/external loopback capabilities external address detection interface (eadi ? ) for external hardware address filtering in bridge/router applications jtag boundary scan (ieee 1149.1) test access port interface for board level production test integrated manchester encoder/decoder digital attachment interface (dai ? ) allows by-passing of differential attachment unit interface (aui) supports the following types of network interface: aui to external 10base2, 10base5 or 10base-f mau dai port to external 10base2, 10base5, 10base-t, 10base-f mau general purpose serial interface (gpsi) to external encoding/decoding scheme internal 10base-t transceiver with automatic selection of 10base-t or aui port sleep mode allows reduced power consump- tion for critical battery powered applications 5 mhz-25 mhz system clock speed support for operation in industrial temperature range ( C 40 c to +85 c) available in all three packages general description the media access controller for ethernet (mace) chip is a cmos vlsi device designed to provide flexibility in customized lan design. the mace device is specif- ically designed to address applications where multiple i/o peripherals are present, and a centralized or sys- tem specific dma is required. the high speed, 16-bit synchronous system interface is optimized for an exter- nal dma or i/o processor system, and is similar to many existing peripheral devices, such as scsi and serial link controllers. the mace device is a slave register based peripheral. all transfers to and from the system are performed using simple memory or i/o read and write commands. in conjunction with a user defined dma engine, the mace chip provides an ieee 802.3 interface tailored to a specific application. its superior modular architec- ture and versatile system interface allow the mace device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. table 5 specification number: 79c940-ci (a) rev - page 1 of 13 the 79c940 mace chip is offered in a plastic 79c940 specifcation number 79c940b-ci (a) rev c
page 3 of 13 rochester part number amd part number package temperature am79c940b-16jc am79c940b-16jc ldcc-84, plastic 0 to +70c am79c940b-25jc am79c940b-25jc ldcc-84, plastic 0 to +70c am79c940bjc am79c940bjc ldcc-84, plastic 0 to +70c am79c940bji am79c940bji ldcc-84, plastic -40 to +85c am79c940bkc am79c940bkc tpak-100, plastic 0 to +70c am79c940bkc/w am79c940bkc/w qfp-100, plastic 0 to +70c am79c940bki am79c940bki tpak-100, plastic -40 to +85c am79c940bki/w am79c940bki/w qfp-100, plastic -40 to +85c am79c940bvc am79c940bvc tpak-80, plastic 0 to +70c am79c940bvc/w am79c940bvc/w tqfp-80, plastic 0 to +70c am79c940bvi am79c940bvi tpak-80, plastic -40 to +85c am79c940bvi/w am79c940bvi/w tqfp-80, plastic -40 to +85c rochester ordering guide *most products can also be offered as rohs compliant, designated by a Cg suffx. please contact factory for more information. 79c940 specifcation number 79c940b-ci (a) rev c
page 4 of 13 am79c940 7 connection diagrams pl 084 plcc package 1 2 3 81 82 83 84 6 7 8 94 5 80 76 77 78 79 75 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 43 42 41 40 47 46 45 44 37 36 35 34 39 38 33 48 52 51 50 49 10 22 11 32 53 74 srdclk eam/r srd sf/bd reset sleep dv dd intr tc dbus0 dv ss dbus1 dbus2 dbus3 dbus4 dv ss dbus5 dbus6 dbus7 dbus8 dbus9 xtal2 av ss xtal1 av dd txd+ txp+ txd- txp- av dd rxd+ rxd- dv dd tdi dv ss tck tms tdo lnkst rxpol cs r/ w rxcrs rxdat clsn txen/ txen stdclk dv ss txdat- txdat+ dv ss edsel dxcvr dv dd av dd ci+ ci- di+ di- av dd do+ do- av ss dbus10 dbus11 dbus12 dbus13 dv dd dbus14 dbus15 dv ss eof dtv fds be0 be1 sclk tdtreq rdtreq add0 add1 add2 add3 add4 am79c940jc mace 16235d-2 table 5 specification number: 79c940-ci (a) rev - page 3 of 13 79c940jc mace 79c940 specifcation number 79c940b-ci (a) rev c
page 5 of 13 8 am79c940 connection diagrams pqr100 pqfp package rxcrs rxdat clsn txen/txen stdclk dv ss txdat- txdat+ dv ss edsel dxcvr dv dd av dd ci+ ci- di+ di- av dd do+ do- 28 29 30 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 99 98 100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 81 83 tck tms tdo lnkst rxpol cs r/w nc nc nc nc av ss nc nc nc xtal2 av ss xtal1 av dd txd+ txp+ txd txp av dd rxd+ rxd dv dd tdi dv ss nc 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 nc nc nc nc srdclk eam/r srd sf/bd reset sleep dv dd intr tc dbus0 dv ss dbus1 dbus2 dbus3 dbus4 dv ss dbus5 dbus6 dbus7 dbus8 dbus9 nc nc nc dbus10 nc dbus11 dbus12 dbus13 dv dd dbus14 dbus15 dv ss eof dtv fds be0 be1 sclk tdtreq rdtreq add0 add1 add2 add3 add4 mace am79c940kc 16235d-3 table 5 specification number: 79c940-ci (a) rev - page 4 of 13 mace 79c940kc 79c940 specifcation number 79c940b-ci (a) rev c
page 6 of 13 am79c940 9 connection diagrams pqt080 tqfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 srdclk eam/r sf/bd reset sleep dv dd intr tc dbus0 dv ss dbus1 dbus2 dbus3 dbus4 dv ss dbus5 dbus6 dbus7 dbus8 dbus9 xtal2 av ss xtal1 av dd txd+ txp+ txd- txp- av dd rxd+ rxd- dv dd tdi dv ss tck tms td0 lnkst cs r/w dbus10 dbus11 dbus12 dbus13 dv dd dbus14 dbus15 dv ss eof fds be0 be1 sclk tdtreq rdtreq add0 add1 add2 add3 add4 rxcrs rxdat clsn txen/ stdclk dv ss txdat+ dv ss edsel dxcvr dv dd av dd ci+ ci- di+ di- av dd do+ do- av ss mace am79c940vc notes: four pin functions available on the plcc and pqfp packages are not available with the tqfp package. (see full data sheet for description of pins not included with the 80-pin tqfp package. in particular, see section pin functions not available with the 80-pin tqfp package.) 16235d-4 table 5 specification number: 79c940-ci (a) rev - page 5 of 13 mace 79c940vc 79c940 specifcation number 79c940b-ci (a) rev c
page 7 of 13 90 absolute maximum ratings storage temperature . . . . . . . . . . . . -65 c to +150 c ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . under bias . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c supply voltage to avss or dvss (avdd, dvdd) . . . . . . . . . . .-0.3 v to +6.0 v stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute max- imum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . .0 c to +70 c industrial (i) devices ambient temperature (t a ) . . . . . . . . . ? 40 c to +85 c v cc supply voltages . . . . . . . . . . . . . . . . . . . . . . (avdd, dvdd) 5 v 5% all inputs within the range: . . avdd ? 0.5 v vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . avss + 0.5 v, or . . . . . . . . . . . . . . . . . . . . . . . . . dv dd ? 0.5 v vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .dv ss + 0.5 v operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics (unless otherwise noted, parametric values are the same between commercial devices and industrial devices.) parameter symbol parameter description test conditions min max unit v il input low voltage 0.8 v v ih input high voltage 2.0 v v ilx xtal1 input low voltage (external clock signal) v ss = 0.0 v ? 0.5 0.8 v v ihx xtal1 input high voltage (external clock signal) v ss = 0.0 v v dd ? 0.8 v dd+ 0.5 v v ol output low voltage i ol = 3.2 ma 0.45 v v oh output high voltage i oh = -0.4 ma (note 1) 2.4 v i il1 input leakage current v dd = 5 v, v in = 0 v (note 2) ? 10 10 a i il2 input leakage current v dd = 5 v, v in = 0 v (note 2) ? 200 200 a i ih input leakage current v dd = 5 v, v in = 2.7 v (note 3) ? 100 a i iaxd input current at di+ and di ? ? 1 v < v in < av dd + 0.5 v ? 500 +500 a i iaxc input current at ci+ and ci ? ? 1 v < v in < av dd + 0.5 v ? 500 +500 a i ilxn xtal1 input low current during normal operation v in = 0 v sleep = high ? 92 (note 9) a i ihxn xtal1 input high current during normal operation v in = 5.5 v sleep = high 92 (note 10) a i ilxs xtal1 input low current during sleep v in = 0 v sleep = low <10 a i ihxs xtal1 input high current during sleep v in = 5.5 v sleep = low 410 a i oz output leakage current 0.4 v < v out < v dd (note 4) ? 10 10 a v aod differential output voltage |(do+) ? (do ? )| r l = 78 ? 630 1200 mv v aodoff transmit differential output idle voltage r l = 78 ? (note 5) ? 40 +40 mv table 5 specification number: 79c940-ci (a) rev - page 7 of 13 79c940 specifcation number 79c940b-ci (a) rev c
page 8 of 13 91 dc characteristics (continued) parameter symbol parameter description test conditions min max unit i aodoff transmit differential output idle current r l = 78 ? ? 1 +1 ma v aocm do common mode output voltage r l = 78 ? 2.5 avdd v v od i do differential output voltage imbalance r l = 78 ? (note 6) ? 25 25 mv v ath receive data differential input threshold r l = 78 ? (note 6) ? 35 35 mv v asq di and ci differential input threshold squelch r l = 78 ? (note 6) ? 160 ? 275 mv v irdvd di and ci differential mode input voltage range 1.5 v v icm di and ci input bias voltage i in = 0 ma av dd ? 3.0 av dd ? 0.8 v v opd di undershoot voltage at zero differential on transmit return to zero (etd) (note 5) ? 100 mv i dd power supply current sclk = 25 mhz xtal1 = 20 mhz 75 ma i ddsleep power supply current sleep asserted, awake = 0 rwake = 1 (note 7) 100 a i ddsleep power supply current sleep asserted, awake = 1 rwake = 0 (note 7) 10 ma i ddsleep power supply current sleep asserted, awake = 0 rwake = 1 (note 7) 20 ma twisted pair interface i irxd input current at rxd av ss < v in < av dd ? 500 500 a r rxd rxd differential input resistance (note 8) 10 k ? v tivb rxd , rxd ? open circuit input voltage (bias) i in = 0 ma av dd ? 3.0 av dd ? 1.5 v v tidv differential mode input voltage range (rxd ) av dd = +5v ? 3.1 +3.1 v v tsq+ rxd positive squelch threshold (peak) sinusoid 5 mhz f 10 mhz 300 520 mv v tsq ? rxd negative squelch threshold (peak) sinusoid 5 mhz f 10 mhz ? 520 ? 300 mv v ths+ rxd post-squelch positive threshold (peak) sinusoid 5 mhz f 10 mhz 150 293 mv v ths ? rxd post-squelch negative threshold) (peak) sinusoid 5 mhz f 10 mhz ? 293 ? 150 mv v ltsq+ rxd positive squelch threshold (peak) lrt = low 180 312 mv v ltsq ? rxd negative squelch threshold (peak) lrt = low ? 312 ? 180 mv v lths+ rxd post-squelch positive threshold (peak) lrt = low 90 156 mv table 5 specification number: 79c940-ci (a) rev - page 8 of 13 79c940 specifcation number 79c940b-ci (a) rev c
page 9 of 13 92 dc characteristics (continued) notes: 1. v oh does not apply to open-drain output pins. 2. i il1 and i il2 applies to all input only pins except di , ci , and xtal1. i il1 = add4 C 0, be 1 C 0, cs , eam/r , fds , reset , rxdat, r/w, sclk. i il2 = tc , tdi, tck, tms. 3. specified for input only pins with internal pull-ups: tc, tdi, tck, tms. 4. i oz applies to all three-state output pins and bi-directional pins. 5. test not implemented to data sheet specification. 6. tested, but to values in excess of limits. test accuracy not sufficient to allow screening guard bands. 7. during the activation of sleep : C the following pins are placed in a high impedance state: srd, sf/bd, txdat, dxcvr, dtv , tdtreq , rdtreq , ntr and tdo. C the following i/o pins are placed in a high impedance mode and have their internal ttl level translators disabled: dbus15 C 0, eof , srdclk, rxcrs, rxdat, clsn, txen , stdclk and txdat+. C the following input pin has its internal pull-up and ttl level translator disabled: tc . C the following input pins have their internal ttl level translators disabled and do not have internal pull-ups: cs , fds , r/w , add4-0, sclk, be0 , be1 and eam/r . C the following pins are pulled low: xtal1 (xtal2 feedback is cut off from xtal1), txd+, txd C , txp+, txp C , do+ and do. C the following pins have their input voltage bias disabled: di+, di, ci+ and ci. C awake and rwake are reset to zero. i ddsleep, with either awake set or rwake set, will be much higher and its value remains to be determined. 8. parameter not tested. 9. for industrial temperature version, max value is C 150 a. 10. for industrial temperature version, max value is +150 a. parameter symbol parameter description test conditions min max unit v lths ? rxd post-squelch negative threshold (peak) lrt = low ? 156 ? 90 mv v rxdth rxd switching threshold (note 4) ? 35 35 mv v txh txd and txd output high voltage dv ss = 0v dv dd ? 0.6 dv dd v v txl txd and txd output low voltage dv dd = +5v dv ss dv ss + 0.6 v v txi txd and txd differential output voltage imbalance ? 40 +40 mv v txoff txd and txd idle output voltage dv dd = +5v 40 mv r tx txd differential driver output impedance (note 8) 40 ? txd differential driver output impedance (note 8) 80 ? table 5 specification number: 79c940-ci (a) rev - page 9 of 13 79c940 specifcation number 79c940b-ci (a) rev c
page 10 of 13 93 ac characteristics (unless otherwise noted, parametric values are the same between commercial devices and industrial devices.) notes: 1. the following biu timing assumes that edsel = 1. therefore, these parameters are specified with respect to the falling edge of sclk (sclk ). if edsel = 0, the same parameters apply but should be referenced to the rising edge of sclk ). 2. tested with c l set at 100 pf and derated to support the indicated distributed capacitive load. see the biu output valid delay vs. load chart. 3. guaranteed by design C not tested. 4. t datd is defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead. no. parameter symbol parameter description test conditions min (ns) max (ns) clock and reset timing 1t sclk sclk period 40 1000 2t sclkl sclk low pulse width 0.4*t sclk 0.6*t sclk 3t sclkh sclk high pulse width 0.4*t sclk 0.6*t sclk 4t sclkr sclk rise time 5 5t sclkf sclk fall time 5 6t rst reset pulse width 15*t sclk 7t bt network bit time (bt)=2*tx1 or tstdc 99 101 internal mendec clock timing 9t x1 xtal1 period 49.995 50.005 11 t x1h xtal1 high pulse width 20 12 t x1l xtal1 low pulse width 20 13 t x1r xtal1 rise time 5 14 t x1f xtal1 fall time 5 biu timing (note 1) 31 t adds address valid setup to sclk 9 32 t addh address valid hold after sclk 2 1. 33 t slvs cs or fds and tc , be 1 ? 0, r/w setup to sclk 9 34 t slvh cs or fds and tc , be 1 ? 0, r/w hold after sclk 2 35 t datd data out valid delay from sclk c l = 100 pf (note 2) 32 36 t dath data out valid hold from sclk 6 37 t dtvd dtv valid delay from sclk c l = 100 pf (note 2) 32 38 t dtvh dtv valid hold after sclk 6 39 t eofd eof valid delay from sclk c l = 100 pf (note 2) 32 40 t eofh eof output valid hold after sclk 6 41 t csis cs inactive prior to sclk 9 42 t eofs eof input valid setup to sclk 9 43 t eofh eof input valid hold after sclk 2 44 t rdtd rdtreq valid delay from sclk c l = 100 pf (note 2) 32 45 t rdth rdtreq input valid hold after sclk 6 46 t tdtd tdtreq valid delay from sclk c l = 100 pf (note 2) 32 47 t tdth tdtreq input valid hold after sclk 6 48 t dats data in valid setup to sclk 9 49 t datih data in valid setup after sclk 2 50 t date data output enable delay from sclk (note 3) 0 51 t datd data output disable delay from sclk (note 3, 4) 25 table 5 specification number: 79c940-ci (a) rev - page 10 of 13 79c940 specifcation number 79c940b-ci (a) rev c
page 11 of 13 94 ac characteristics (continued) no. parameter symbol parameter description test conditions min (ns) max (ns) aui timing 53 t dotd xtal1 (externally driven) to do ???? 100 54 t dotr do rise time (10% to 90%) 2.5 5.0 55 t dotf do fall time (10% to 90%) 2.5 5.0 56 t doetm do rise and fall mismatch 1 57 t doetd do end of transmit delimiter 200 375 58 t pwrdi di pulse width to reject |input| > | vasq | 15 59 t pwodi di pulse width to turn on internal di carrier sense |input| > | vasq | 45 60 t pwmdi di pulse width to maintain internal di carrier sense on |input| > | vasq | 45 136 61 t pwkdi di pulse width to turn internal di carrier sense off |input| > | vasq | 200 62 t pwrci ci pulse width to reject |input| > | vasq | 10 63 t pwoci ci pulse width to turn on internal sqe sense |input| > | vasq | 26 64 t pwmci ci pulse width to maintain internal sqe sense on |input| > | vasq | 26 90 65 t pwkci ci pulse width to turn internal sqe sense off |input| > | vasq | 160 66 t sqed ci sqe test delay from o inactive |input| > | vasq | 67 t sqel ci sqe test length |input| > | vasq | 79 t clshi clsn high time t stdc + 30 80 t txh txen or do hold time from clsn |input| > | vasq | 32*t stdc 96*t stdc dai port timing 70 t txend stdclk delay to txen c l = 50 pf 70 72 t txdd stdclk delay to txdat change c l = 50 pf 70 80 t txh txen or txdat hold time from clsn 32*t stdc 96*t stdc 95 t dotf mismatch in stdclk to txen and txdat change 15 96 t txdtr txdat rise time see note 1 5 97 t txdtf txdat fall time see note 1 5 98 t txdtm txdat rise and fall mismatch see note 1 1 99 t txenetd txen end of transmit delimiter 250 350 100 t frxdd first rxdat delay to rxcrs 100 101 t lrxdd last rxdat delay to rxcrs 120 102 t crsclsd rxcrs delay to clsn (txen = 0) 100 table 5 specification number: 79c940-ci (a) rev - page 11 of 13 79c940 specifcation number 79c940b-ci (a) rev c
page 12 of 13 95 ac characteristics (continued) note: 1. not tested but data available upon request. no. parameter symbol parameter description test conditions min (ns) max (ns) gpsi clock timing 17 t stdc stdclk period 99 101 18 t stdcl stdclk low pulse width see note 1 45 19 t stdch stdclk high pulse width 45 20 t stdcr stdclk rise time see note 1 5 21 t stdcf stdclk fall time see note 1 5 22 t srdc srdclk period 85 115 23 t srdch srdclk high pulse width 38 24 t srdcl srdclk low pulse width 38 25 t srdcr srdclk rise time see note 1 5 26 t srdcf srdclk fall time see note 1 5 gpsi timing 70 t txend stdclk delay to txen (c l = 50 pf) 70 71 t txenh txen hold time from stdclk (c l = 50 pf) 5 72 t txdd stdclk delay to txdat+ change (c l = 50 pf) 70 73 t txdh txdat+ hold time from stdclk (c l = 50 pf) 5 74 t rxdr rxdat rise time see note 1 8 75 t rxdf rxdat fall time see note 1 8 76 t rxdh rxdat hold time (srdclk to rxdat change) 25 77 t rxds rxdat setup time (rxdat stable to srdclk ) 0 78 t crsl rxcrs low time t stdc + 20 79 t clshi clsn high time t stdc + 30 80 t txh txen or txdat hold time from clsn 32*t stdc 96*t stdc 81 t crsh rxcrs hold time from srdclk 0 eadi feature timing 85 t dsfbdr srdclk delay to sf/bd 20 86 t dsfbdf srdclk delay to sf/bd 20 87 t eamris eam/r invalid setup prior to srdclk after sfd ? 150 88 t eams eam setup to srdclk at bit 6 of source address byte 1 (match packet) 0 89 t eamr l eam/r low time 200 90 t sfbdhih sf/bd high hold from last srdclk 100 91 t ears ear setup srdclk at bit 6 of message byte 64 (reject normal packet) 0 table 5 specification number: 79c940-ci (a) rev - page 12 of 13 79c940 specifcation number 79c940b-ci (a) rev c
page 13 of 13 96 ac characteristics (continued) note: 1. not tested but data available upon request. no. parameter symbol parameter description test conditions min max ieee 1149.1 timing 109 t tclk tck period, 50% duty cycle (+5%) 100 110 t su1 tms setup to tck 8 111 t su2 tdi setup to tck 5 112 t hd1 tms hold time from tck 5 113 t hd2 tdi hold time from tck 10 114 t d1 tck delay to tdo 30 115 t d2 tck delay to system output 35 10base C t transmit timing min max 125 t tetd transmit start of idle 250 350 126 t tr transmitter rise time (10% to 90%) 5.5 127 t tf transmitter fall time (90% to 10%) 5.5 128 t tm transmitter rise and fall time mismatch 1 129 t xmton xmt# asserted delay 100 130 t xmtoff xmt# de-asserted delay tbd tbd 131 t perlp idle signal period 8 24 132 t pwlp idle link pulse width (note 1) 75 120 133 t pwplp predistortion idle link pulse width (note 1) 45 55 134 t ja transmit jabber activation time 20 150 135 t jr transmit jabber reset time 250 750 136 t jrec transmit jabber recovery time (minimum time gap between transmitted packets to prevent jabber activation) 1.0 10base C t receive timing 140 t pwnrd rxd pulse width not to turn off internal carrier sense vin > vths (min) 136 ? 141 t pwroff rxd pulse width to turn off vin> vths (min) 200 142 t retd receive start of idle 200 143 t rcvon rcv# asserted delay t ron ? 50 t ron ? 100 144 t rcvoff rcv# de-asserted delay tbd tbd table 5 specification number: 79c940-ci (a) rev - page 13 of 13 rochester electronics guarantees performance of its semiconductor products to the original oem specifcations. typical values are for reference purposes only. certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. rochester electronics reserves the right to make changes without further notice to any specifcation herein. 79c940 specifcation number 79c940b-ci (a) rev c

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